Teledyne e2v: Boost dynamic performance of a broadband ADC by some 10 dBFS instantly with spur reduction IP
- Written by Teledyne e2v
- The new EV12AQ600/605-ADX4 device options now feature an integrated ADX4 license key enabling enhanced dynamics when operating at up to a peak of 6.4 GS/s (single channel mode).
- ADX4 - a post-processing algorithm compatible with Xilinx Kintex® Ultrascale™ FPGAs delivers up to 10 dBFS of SFDR dynamic spurs reduction and close to 1 effective bit extra resolution in broadband applications.
- Time-interleaving, whilst providing a conceptually easy to comprehend sample rate boost, is challenging to achieve at extended resolutions and wide bandwidths.
References
- ^ Media OutReach (www.media-outreach.com)
- ^ Teledyne e2v EV12AQ600/5-ADX4 datasheet (semiconductors.teledyneimaging.com)
- ^ Teledyne e2v EV12AQ600/5 product page (semiconductors.teledyneimaging.com)
- ^ Video link: Learn time-interleaved EV12AQ600 ADC mismatch error correction (www.youtube.com)
Authors: Teledyne e2v
Read more https://www.media-outreach.com/news/hong-kong/2022/06/17/143607/